Technology Roundtables
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L-R: Synopsys’ Roosendaal; ASE’s Chen; Amkor’s Kelly; Promex’s Otte.
Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, hybrid bonding, and new materials with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion. To view part one of this discussion, click here. Part two is here.
Benefits And Challenges In Multi-Die Assemblies
April 2, 2025 - Courtesy of Semiconductor Engineering
L-R: Cadence’s Young; Synopsys’ Stahl; Siemens’ Munsey; ChipAgents’ Wang; Theodore Wilson.
Experts At The Table: AI is starting to impact several parts of the EDA design and verification flows, but so far these improvements are isolated to a single tool or small flows provided by a single company. What is required is a digital twin of the development process itself, on which AI can operate. Semiconductor Engineering sat down with a panel of experts, including Johannes Stahl, senior director of product line management for the Systems Design Group at Synopsys; Michael Young, director of product marketing for Cadence; William Wang, founder and CEO of ChipAgents and professor at the University of California, Santa Barbara; Theodore Wilson, a verification expert pushing for this development; and Michael Munsey, vice president of semiconductor industry for Siemens Digital Industries Software. What follows are excerpts from that conversation.
Digital Twins For Design And Verification Workflows
March 27, 2025 - Courtesy of Semiconductor Engineering
L-R: Arteris’ Rensch, Cadence’s Graham, Siemens’ Chobisa, Synopsys’ Schirrmeister
Experts at the Table: The pressure on verification engineers to ensure the functional correctness of devices has increased exponentially as chips have gotten more complex and evolved into SoC, 3D-ICs, multi-die chiplets and beyond. Semiconductor Engineering sat down with a panel of experts, which included Josh Rensch, director of application engineering at Arteris; Matt Graham, senior group director verification software product management at Cadence; Vijay Chobisa, senior director for product management for the Veloce hardware-assisted verification platform at Siemens EDA; and Frank Schirrmeister, executive director, strategic programs, System Solutions at Synopsys. What follows are excerpts of that discussion.
The Evolving Role Of AI In Verification
March 25, 2025 - Courtesy of Semiconductor Engineering
L-R: ProteanTecs’ Burlak, DR Yield’s Rathei, Synopsys’ de Vries, PDF Solutions’ Holt
Experts at the Table: Semiconductor Engineering sat down to discuss the benefits of incorporating financial data into fab floor decision-making, including what kind of cost data is most useful, with Dieter Rathei, CEO of DR Yield; Jon Holt, senior director of product management at PDF Solutions, Alex Burlak, vice president of advanced analytics and test at proteanTecs; and Dirk de Vries, technical program manager and senior architect at Synopsys. What follows are excerpts of that conversation.
Cutting IC Manufacturing Costs By Combining Data
March 11, 2025 - Courtesy of Semiconductor Engineering
L-R: Cadence’s Metcalfe, Eliyan’s Ziai, Keysight’s Petr, Siemens’ Wiens, Synopsys’ Rangarajan
Experts at the Table: LLMs and other generative AI programs are a long way away from being able to design entire chips on their own from scratch, but the emergence of the tech has still raised some genuine concerns. Semiconductor Engineering sat down with a panel of experts, which included Rod Metcalfe, product management group director at Cadence; Syrus Ziai, vice-president of engineering at Eliyan; Alexander Petr, a senior director at Keysight EDA; David Wiens, product marketing manager at Siemens; and Geetha Rangarajan, director of product management for generative AI at Synopsys to talk about what keeps them up at night when it comes to AI. What follows are excerpts of that discussion.
What Scares Chip Engineers About Generative AI
February 26, 2025 - Courtesy of Semiconductor Engineering
L-R: Teradyne’s Hurtarte, Synopsys’ Ganta, Advantest’s Armstrong, Siemens EDA’s Harrison
Experts at the Table: Semiconductor Engineering sat down to discuss advances in packaging with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion.
Optimizing DFT With AI And BiST
February 12, 2025 - Courtesy of Semiconductor Engineering
L-R: Synopsys’ Roosendaal, ASE’s Chen; Amkor’s Kelly, Promex’s Otte
Experts at the Table: Semiconductor Engineering sat down to discuss advances in packaging with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion.
Advanced Packaging Moving At Breakneck Pace
January 29, 2025 - Courtesy of Semiconductor Engineering